module ODDR_rtl (
    input               C ,
    input               SR ,

    input               D1 ,
    input               D2 ,
    output              Q
) ;
    reg [1:0] Data_temp ;

    always @(posedge C or posedge SR) begin
        if(SR)
            Data_temp <= 2'b0 ;
        else
            Data_temp <= {D1, D2} ;
    end


    reg clk_pos ;
    reg clk_neg ;
    wire clk_sel;
    assign clk_sel = clk_pos ^ clk_neg ;
    always @(posedge C or posedge SR) begin
        if(SR)
            clk_pos <= 1'b0 ;
        else
            clk_pos <= ~clk_pos ;
    end
    always @(negedge C or posedge SR) begin
        if(SR)
            clk_neg <= 1'b0 ;
        else 
            clk_neg <= ~clk_neg ; 
    end

`ifdef FPGA_MODE
    assign Q = (clk_sel)?Data_temp[1]:Data_temp[0] ;
`else
    assign Q = (clk_sel)?Data_temp[0]:Data_temp[1] ;
 `endif

endmodule

